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mode item symbol min typ max unit write mode (refer to fig-6) e cycle time tc 500 - - ns e rise / fall time tr,tf - - 25 e pulse width (high, low) tw 220 - - r/w and rs setup time tsu1 40 - - r/w and rs hold time th1 10 - - data setup time tsu260 - - data hold time th210 - - read mode (refer to fig-7) e cycle time tc 500 - - ns e rise / fall time tr,tf - - 25 e pulse width (high, low) tw 220 - - r/w and rs setup time tsu 40 - - r/w and rs hold time th 10 - - data output delay time t d --120 data hold time t dh 20- -
fig-6. write mode timing diagram th1 tw v ih1 tr t su2 th2 tf th1 v il1 valid data tc v il1 t su1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v il1 rs r/w e db0~db7 fig-7. read mode timing diagram th tw v ih1 tr t dh tf th v il1 valid data tc v il1 t su v ih1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 v il1 v ih1 rs r/w e db0~db7 t d
instruction table * note : when you make an mpu program with checking the busy flag (db7), it must be necessary 1/2fosc for executing the next instruction by falling e signal after the busy flag (db7) goes to 0. instruction instruction code description execution time (fosc = 270 khz) rs r/wdb7db6db5db4db3db2db1db0 clear display 0000000001 write 20h to ddram and set ddram address to 00h from ac. 1.53 ms return home 000000001 set ddram address to 00h from ac and return cursor to its original position if shifted. 1.53 ms entry mode set 00000001i/dsh assign cursor moving direction and enable the shift of entire display . 39 s display on/ off control 0000001dcb set display (d), cursor (c), and blinking of cursor (b) on/off control bit. 39 s cursor or display shift 0 0 0 0 0 1 s/c r/l set cursor moving and display shift control bit, and the direction, without changing of ddram data. 39 s function set 00001dlnf set interface data length (dl : 4-bit/8- bit), numbers of display line (n : 1-line/ 2-line, display font type (f:0 ...) 39 s set cgram address 0 0 0 1 ac5ac4ac3ac2ac1ac0 set cgram address in address counter. 39 s set ddram address 0 0 1 ac6ac5ac4ac3ac2ac1ac0 set ddram address in address counter. 39 s read busy flag and address 0 1 bf ac6ac5ac4ac3ac2ac1ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can also be read. 0 s write data to ram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 43 s read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 43 s
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